Dual 12-bit 2.5-GSPS ADC

Features

• Differential analog and clock inputs with on-chip termination.
• On-chip reference and bias circuitry.
• Built-in clock phase generation.

Benefits

• Ultra high sample rate
• Low bit-error-rate (1E-18)
• High input bandwidth (2 GHz)

Deliverables

• GDS2
• CDL
• LEF
• RTL for calibration
• Verilog-A model
• (US export restrictions apply)

Applications

• High-bandwidth communications
• Test & Measurement
• Radar / Lidar

Block Diagram of the Dual 12-bit 2.5-GSPS ADC IP Core

• see the entire Dual 12-bit 2.5-GSPS ADC datasheet
• get in contact with Dual 12-bit 2.5-GSPS ADC Supplier