The dual, 12-bit, 2-5-GSPS ADC has a build-in Track & Hold and an interleaved quantizer array for power-efficiency and low bit-error-rate. The ADC is self-calibrated for matching and linearity.
- Differential analog and clock inputs with on-chip termination.
- On-chip reference and bias circuitry.
- Built-in clock phase generation.
- Ultra high sample rate
- Low bit-error-rate (1E-18)
- High input bandwidth (2 GHz)
- RTL for calibration
- Verilog-A model
- (US export restrictions apply)
- High-bandwidth communications
- Test & Measurement
- Radar / Lidar
Block Diagram of the Dual 12-bit 2.5-GSPS ADC IP Core