English
You are here:
Dual 12-bit 2.5-GSPS ADC
The dual, 12-bit, 2-5-GSPS ADC has a build-in Track & Hold and an interleaved quantizer array for power-efficiency and low bit-error-rate. The ADC is self-calibrated for matching and linearity.
Features
- Differential analog and clock inputs with on-chip termination.
- On-chip reference and bias circuitry.
- Built-in clock phase generation.
Benefits
- Ultra high sample rate
- Low bit-error-rate (1E-18)
- High input bandwidth (2 GHz)
Deliverables
- GDS2
- CDL
- LEF
- RTL for calibration
- Verilog-A model
- (US export restrictions apply)
Applications
- High-bandwidth communications
- Test & Measurement
- Radar / Lidar
Block Diagram of the Dual 12-bit 2.5-GSPS ADC IP Core
View Dual 12-bit 2.5-GSPS ADC full description to...
- see the entire Dual 12-bit 2.5-GSPS ADC datasheet
- get in contact with Dual 12-bit 2.5-GSPS ADC Supplier
12-bit ADC
- 10-bit, 12-bit, 14-bit, Low Speed SAR ADC in TSMC (180nm, 90nm, 65nm, 55nm, 40nm, 28nm, 16nm, 12nm)
- 12-bit, 8 GSPS High Performance RF ADC in 16nm CMOS
- 12 Bit 40 MS/s Pipeline ADC
- 12 Bit 20 MS/s Pipeline ADC
- 12-bit 424MS/s High-Speed SAR ADC
- 800MHz, 12-bit High Speed Delta Sigma ADC for 5G, LiDAR and Imaging