The dual 2.6 GHz Analog to Digital Converter core utilizes a 4-stage interpolating flash type architecture. The core incorporates two ADCs, two 48-bit input registers, and two 1:8 data de-serializers. The dual ADCs can support sample rates up to 2.6 GHz at input bandwidths of 900 MHz. The output of the core incorporates a 1:8 de-serializer interface which can communicate with synchronous interface protocols at 1/8 the ADC sample frequency. The ADCs are internally synchronized for optimum performance for use in I and Q modulation communication systems. The core is optimized for power sensitive applications and features two power saving modes of operation. Input muxes and an integrated analog test bus have been added for testability and debug.
- Dual 2.6 GHz 6-bit ADCs
- 5.4 ENOB (typ) @ 2.6 GHz
- Input bandwidth is 900 MHz max.
- Integrated bandgap, bias generator, and voltage regulator
- One external resistor required for the bias generator
- Two 1:8 Data Deserializer
- Targeted for TSMC 65nm LP CMOS technology
- Specification/Datasheet with Integration Guidelines,
- Verilog Model (.v), Abstract (.LEF),
- LVS Netlist (.cdl), Timing model (.lib),
- GDSII (with associated stream map file),
- Physical Verification Summary Files