The dual 2.6 GHz DAC front end core utilizes a programmable current steering architecture. The core incorporates two DACs, two 48-bit input registers, 5 bit gain control, and two 8:1 data serializers. The dual DACs can support sample rates up to 2.6 GHz and output bandwidths of 900 MHz. The interface incorporates 48-bit input registers to communicate with synchronous interface protocols at 1/8 the DAC sample frequency. The DACs are internally synchronized for optimum performance for use in I and Q modulation communication systems.