4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
Dual-issue Linux-capable RISC-V core
The core supports wait for interrupt (WFI) and non-maskable interrupts (NMI) and works with a platform-level interrupt controller (PLIC). It has an AXI-5 128-bit bus interface.
The A730 core has a wide range of configuration options.
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Block Diagram of the Dual-issue Linux-capable RISC-V core IP Core
![Dual-issue Linux-capable RISC-V core Block Diagam](http://www.design-reuse.com/sip/blockdiagram/53206/20231023010858-main-Artboard-1-100.jpg)
RISC-V IP
- RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
- ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
- ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications
- 64-bit RISC-V Application Processor Core