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Dual Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 80 k
Foundry sponsored - Dual Port SRAM compiler - TSMC 90 nm LPeF - Memory otimized for high density and low power - compiler range up to 80 k
Features
- Reduced the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Routing allowed upwards from Metal 4, Support Metal 5 top Metal option
- Extend the battery life
- Ultra low leakage thanks to careful design strcutures ▪ Optional byte write and bit wise write capability
- Data retention mode
- Make the integration easier
- Wide flexibility for words and bits per word
- Two completely independent Read/Write Ports which implements full Dual-Port (2RW) functionality
- Enable right on 1st pass design, the Dolphin integration quality
- Complete mismatch validation of the memory architecture taking in account local and global dispersion
- Extended validation for high coverage rate of the compiler
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- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
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