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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
Dual Port SRAM compiler - TSMC 40 nm uLP - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
Features
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
- Dynamic power reduction thanks to segment partitioning
- Data retention mode at 1.2 V +/-10%, 1.1 V +/-10%, 0.9 V +/-10% and 0.6 V (optional) to drastically divide the leakage compared to simple stand by mode
- Make the integration easier
- Wide flexibility for words and bits per word
- Flexible segment partitioning (Selectable 1-4 segments) allow the user to choose the best optimization between area, speed & power for his application
- Two completely independent Read/Write Ports which implements full Dual-Port (2RW) functionality
- Embedded Extinction and Retention Switches (ERS)
- Enable right on 1st pass design, the Dolphin integration quality
- Complete mismatch validation of the memory architecture taking in account local and global dispersion
- Extended validation for high coverage rate of the compiler
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SRAM
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- General purpose microprocessor with integrated SRAM controller and real time execution unit, optimized for low cost, low power microcontroller applications
- MCU with integrated 64-bit SRAM controller, Memory Protection Unit and real-time, low latency execution unit, optimized for low cost, low power microcontroller and embedded applications
- Single Port, Ultra High Speed, GF 22FDX, SRAM Memory Compiler
- 32-bit SRAM/PROM Controller
- Low power, high speed, and high density configurable SRAM