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Dual-Rail SRAM Globalfoundries 22FDX
Ultra-low voltage logic designs utilizing adaptive body biasing demand for dense SRAM solutions which fully integrates in the ABB aware implementation and sign-off flow of the Racyics® ABB platform solution. The Racyics® dual-rail SRAM supports ultra-low voltage core logic operation down to 0.40V while operating dense, low leakage standard bit cells from a 0.80V memory supply.
Features
- Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
- Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
- Direct interfacing to ULV Racyics® ABB digital standard cell domains without additional level shifters
- Fullset of characterization corners for -40°C to 125°C temperature range for Racyics® ABB aware timing and power sign-off
- Full statistical LVF characterization for low voltage operation
- Production test methodology available for ABB
Deliverables
- Verilog simulation models
- .libidb timing (NLDM, CCS, LVF) and power models
- .lef layout abstract views
- Milkyway database
- GOSH layouts
- LVS netlist
Block Diagram of the Dual-Rail SRAM Globalfoundries 22FDX IP Core
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Dual-Rail SP SRAM IP
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Dual Port SRAM Compiler IP, UMC 0.13um SP/FSG process
- Dual Port SRAM Compiler IP, UMC 65nm SP process
- Dual Port SRAM Compiler IP, UMC 0.11um SP process
- 55 SP Dual Port SRAM compiler with 1P4M metal option