This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the transfer of digital display data between a Timing Control source (TCON) and Column Drivers of a Flat Panel Display.
The transmitter converts up to 24bits DDR CMOS data (single pixel 18bits, single pixel 24bits, dual pixel 18bits, dual pixel 24bits color) into 24 RSDS, (Reduced Swing Differential Signaling) data streams.
At a maximum dual pixel rate of 150Mhz, RSDS data line speed is 300Mbps, providing a total throughput of 7.2Gbps (900MegaBytes per second).
All the data input/output are independent from each other and can be assigned following any partitioning to support all LCD and Plasma display panel system architectures. (RGB, front/back, even/odd, mixed RGB etc…)
Each pixel channel has 2 identical clock outputs. Strength of the RSDS I/Os can be adjusted from 2mA nominal to 4mA in order to support both 100 and 50 ohm termination.
For convenient routing when TCON is mounted on top or bottom of a display panel, a selectable output data mapping is usually available. LSB or MSB of both channels can be forced to High-Z in order to support 6-bit data color.
This IP can interface with both 1.8V or 3.3V core logic, giving more flexibility for the design.
Designed for LCD and PLASMA display panels
- • 20 to 150Mhz Pixel rate ( 40 to 300 Mb/s SDR input, 40 to 300 Mb/s DDR output)
- • Complies with RSDS “Intra-Panel” Interface Specification rev1.0, May 2003.
- • 1P6M layout structure based on 0.18um 1P6M generic logic process.
- • 3.3V/1.8V 10% supply voltage, -40/+125C
- • For either 3.3V only or 1.8V/3.3V design.
- • Dual pixel architecture up to 7.2Gbps bandwidth
- • 6x RSDS clock channels
- • Low EMI
- • 8/6 Bit color & reverse output mapping support
- • Self Power-On-Reset feature
- • Precise RSDS clock skew adjustment using DLL
- • Phase-shifted clock output to core to support any additional CD control signals
- • Built-in power pads with ESD protection
- • Low leakage power-down mode <10uA.
- • Low power consumption, [contact us]
- • Very compact cell area : [contact us].
- Low cost IP
- highly adjustable
- customization for your own design
- support full HDTV
- Design kit includes :
- LEF view and abstract gdsII
- Verilog HDL behavioral model
- Liberty (.lib) timing constraints for typical, worse and best corner case
- Full Datasheet /Application Note with integration guidelines document
- Silicon characterization report when available