Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline
The SweRV Core Support Package (SCSP) contains everything needed to deploy a Western Digital SweRV Core™ EH2 core in an integrated circuit providing support for both EDA tool flows and embedded software development. SCSP saves the considerable effort that would be needed to set up EDA flows for the EH2 core from scratch.
The SweRV Core Support Package for the EH2 is available in both basic Free and Pro versions.
The Free version consists of open source deliverables and infrastructure for using open source EDA tools and an SDK. Users can access a forum for support
The Pro version combines open source and commercial deliverables. It provides flows, examples and models for using commercial EDA tools. Codasip provides professional support for this version.
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Block Diagram of the Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline

RISC-V IP
- Intelligent Sensor and Power Management Design Platform
- Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- RISC-V-based SoC template
- Low-power 32-bit RISC-V processor
- Compact, efficient 64-bit RISC-V processor with 5-stage pipeline
- 64-bit RISC-V application processor core with 7-stage pipeline