English
You are here:
Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline
The Western Digital SweRV Core™ EH2 is an RV32IMAC, 9-stage, dual-threaded, dual-issue, superscalar, mostly in-order pipeline with some out-of-order execution capability. Like the EH1 and EL2, it supports optional instruction and data closely coupled memories with ECC protection and optional 2- or 4-way set-associative instruction cache with parity or ECC protection (32- or 64-byte line size). The EH2’s performance is rated at 6.3 CoreMark/MHz. The core has been open sourced through CHIPS Alliance.
The SweRV Core Support Package (SCSP) contains everything needed to deploy a Western Digital SweRV Core™ EH2 core in an integrated circuit providing support for both EDA tool flows and embedded software development. SCSP saves the considerable effort that would be needed to set up EDA flows for the EH2 core from scratch.
The SweRV Core Support Package for the EH2 is available in both basic Free and Pro versions.
The Free version consists of open source deliverables and infrastructure for using open source EDA tools and an SDK. Users can access a forum for support
The Pro version combines open source and commercial deliverables. It provides flows, examples and models for using commercial EDA tools. Codasip provides professional support for this version.
The SweRV Core Support Package (SCSP) contains everything needed to deploy a Western Digital SweRV Core™ EH2 core in an integrated circuit providing support for both EDA tool flows and embedded software development. SCSP saves the considerable effort that would be needed to set up EDA flows for the EH2 core from scratch.
The SweRV Core Support Package for the EH2 is available in both basic Free and Pro versions.
The Free version consists of open source deliverables and infrastructure for using open source EDA tools and an SDK. Users can access a forum for support
The Pro version combines open source and commercial deliverables. It provides flows, examples and models for using commercial EDA tools. Codasip provides professional support for this version.
Features
- SwerRV EH2 Core
- RV32IMAC instructions
- Dual thread
- Dual issue
- 9-stage pipeline
- 4 stall points
- Instruction cache
- 6.3 CoreMarks/MHz
- 0.067mm2 in TSMC 16 nm
- SweRV Core Support Package for EH2 Core
- Free and Pro versions
- Support for open and commercial EDA tools
- Emulation using Digilent FPGA board
- Examples of bare metal and FreeRTOS
- Software
Benefits
- The SCSP provides a low risk way of deploying the SweRV EH2 core with either open source or commercial EDA tools.
- Pre-defined EDA flows with differences between specific EDA tools abstracted from the user.
- The package is complete supporting embedded software development, emulation, implementation and comprehensive debug.
- The offering is flexible depending on the complexity of the EDA flows required.
Deliverables
- SweRV Core Support Package Free Version
- Western Digital EH2 open RTL
- IP-specific flows for open EDA tools
- Western Digital Whisper ISS
- RISC-V GNU toolchain
- Eclipse IDE
- Open OCD debugging tool
- Software examples
- Codasip infrastructure for EDA & IP
- User forum
- SweRV Core Support Package Pro Version contains additionally
- Flows for commercial simulators
- Flows for commercial synthesis tools
- Flows for commercial static code analysis
- Tools and equivalence checking
- Professional support from Codasip
Applications
- High performance 32-bit embedded applications such as storage (NAND flash controllers & SSD), database engines and networking
Block Diagram of the Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline
View Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline full description to...
- see the entire Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline datasheet
- get in contact with Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline Supplier
RISC-V IP
- Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- Low-power 32-bit RISC-V processor
- Compact RISC-V Processor - 32 bit, 3-stage
- RISC-V processor - 32 bit, 5-stage pipeline
- Compact, efficient 64-bit RISC-V processor with 5-stage pipeline
- Single issue, embedded RISC-V core with 4-stage pipeline