Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline

The Western Digital SweRV Core™ EH2 is an RV32IMAC, 9-stage, dual-threaded, dual-issue, superscalar, mostly in-order pipeline with some out-of-order execution capability. Like the EH1 and EL2, it supports optional instruction and data closely coupled memories with ECC protection and optional 2- or 4-way set-associative instruction cache with parity or ECC protection (32- or 64-byte line size). The EH2’s performance is rated at 6.3 CoreMark/MHz. The core has been open sourced through CHIPS Alliance.
The SweRV Core Support Package (SCSP) contains everything needed to deploy a Western Digital SweRV Core™ EH2 core in an integrated circuit providing support for both EDA tool flows and embedded software development. SCSP saves the considerable effort that would be needed to set up EDA flows for the EH2 core from scratch.
The SweRV Core Support Package for the EH2 is available in both basic Free and Pro versions.
The Free version consists of open source deliverables and infrastructure for using open source EDA tools and an SDK. Users can access a forum for support
The Pro version combines open source and commercial deliverables. It provides flows, examples and models for using commercial EDA tools. Codasip provides professional support for this version.

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