Timer and counters are essential in CPU applications. Used to count events, measure time intervals or frequencies, or generate periodic timing events.
The TIMERmodule provides two independent 16-bit timers each with its own 16-bit pre-scaler. An additional pre-scaler is provided for applications where external high frequency events or clocks control the operation. The two timers can be locked for measurements over a given time span. Timer B provides the observation window while Timer A is counting events.
The operating mode of each timer can be selected independently:
- Free running: Timer is reloaded with initial value after counter reaches zero
- One-shot: Timer stops after reaching terminal count
- Window mode: Timer A counts while Timer B generates observation window
Each timer generates an interrupt upon arriving at terminal count zero. A count capture command is available to sample the current count state without interrupting the timer.
- Clock prescaler for external high frequency sources
- Internal or external clock source select
- Supports single-shot, free running and counter mode
- Provides two 16-bit counter /timers with individual 16-bit prescalers
- Two interrupt sources, one for each counter/timer
- Individual counter capture commands
- Supports synchronous bus interfaces such as AMBA APB version 2.0
- Gate-count optimization
- Configurable CPU readback path
- For gate-count optimization, the core can be configured to disable the configuration register read-back path. Synthesis options are included to use the core in 8, 16 and 32-bit systems. With a separate APB wrapper, the core can be used in ARM subsystems.
- VHDL or Verilog RTL Source Code
- Functional Testbench
- Synthesys Script
- Data Sheet
- User Guide
- Hotline Support by means of phone, fax and e-mail
- Industrial control
- CPU subsystems
- System-on-Chip design
- Watchdog or timing reference
Block Diagram of the Dual Timer / Counter with Prescaler IP Core