This state of the art implementation of the AES-GCM algorithm provides privacy and authentication and achieves 10Gbit/sec performance under worst case traffic conditions on modern Xilinx FPGAs with a clock frequency of 156.25MHz.
This is an area optimised version of our AES-GCM-10G product which is suitable for applications such as OTN where key changes are infrequent and the packets to be encrypted are all the same size. The significant area reductions over the standard AES-GCM-10G product are achieved by sharing a single fast encryptor with 20Gbit/sec throughput across two 10Gbit channels in the duplex configuration and precalculating keyschedule information and information for use in the GF-Hash computation in software rather than calculating it on the fly with hardware.
This core is supplied as VHDL source code with a testbench which contains a behavioral model of AES-GCM and self-checks the hardware design against the model on a sequence of random packets.
- Cipher Modes: AES-GCM (as specified in NIST SP800-38D)
- Internal Data Path Width: 128 bits with pipelining
- Functions: Simultaneous Encrypt and Decrypt channels
- Key Lengths: 128 or 256 bits
- IV Length: 96 bits