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Second-Generation Digital Fractional-N PLL for 5G Applications
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DVB-GSE IPv4/IPv6 De-encapsulator
High-throughput, low-latency de-encapsulator IP cores for building DVB-GSE systems. The IP Core Worx DVB-GSE IP cores have been optimised for high performance, and also for DVB-S2/-T2/-C2 implementations that have strict resource/area constraints; for example, FPGA-based systems.
Features
- GSE de-encapsulation and PDU re-assembly for IPv4/IPv6 packets
- Designed for high throughput and low latency
- Supports GSE packet header types for no labels, 6 byte labels, label reuse, and label-based filtering
- Parameterisable MTU’s and SRAM/buffer sizes
- Low (logic and SRAM) resource usage
- Support for both 16200b and 64800b BBFRAME’s, and all DATA FIELD sizes
- AXI4-Stream (8-bit) Interconnect
- Wishbone (SPEC B4) interface for control and packet/device statistics
- Includes BBFRAME parser, stream de-MUX, and de-scrambling cores
- Robust exception handling and with rapid recovery from exceptions (due to overflows & invalid input data)
- FPGA-proven with Xilinx and Microsemi devices
Deliverables
- Netlist or synthesisable RTL source code in VHDL
- Comprehensive verification test bench and vectors in VHDL
- User guides and documentation for integration & configuration
- Top-level entity for a CCM-only system, to aid with evaluation and rapid-prototyping
Block Diagram of the DVB-GSE IPv4/IPv6 De-encapsulator IP Core
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