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MIPI D-PHY 1.5Gbps (4-lanes TX/RX, PLL Integrated) TSMC 28HPM
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DVB-S2 BCH and LDPC Encoder and Decoder
DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites. It was published in 2005, being the first standard of the second generation DVB standards (DVB-S2/DVB-T2/DVB-C2). Because of its capacity-approaching forward error correction, today DVB-S2 is the de-facto standard in satellite communication and other applications. The Creonic DVB-S2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder).
Applications
Satellite communication (Digial Video Broadcasting, Interactive Services, News Gathering, Professional Services)
Applications with highest demands on forward error correction
Applications with the need for a wide range of code rates
Applications
Satellite communication (Digial Video Broadcasting, Interactive Services, News Gathering, Professional Services)
Applications with highest demands on forward error correction
Applications with the need for a wide range of code rates
Features
- Compliant with ETSI 302 307 V1.2.1 (2009-08) (DVB-S2).
- Support for short blocks (16200 bits) and long blocks (64800 bits).
- Support for all modulation schemes (QPSK, 8-PSK, 16-APSK, 32-APSK).
- Support for all interleaving schemes of all modulation schemes.
- Support for all LDPC and BCH codes as defined by the standard.
Benefits
- Decoder contains soft-decision demapper, block deinterleaver, LDPC decoder, BCH decoder, and descrambler.
- Encoder contains scrambler, BCH encoder, LDPC encoder, and block interleaver.
- AXI4-Stream Interface.
- Design-time configuration of throughput for optimal resource utilization.
- Low-power and low-complexity design.
- Burst-to-burst on-the-fly configuration.
- Faster convergence due to layered LDPC decoder architecture.
- Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy.
- Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance.
- Collection of statistic information (number of modified information bits, number of iterations, decoding successful).
- Available for ASIC and FPGAs (Xilinx, Intel).
Deliverables
- Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model.
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