The DVB-S2 Demodulator IP Core implements a DVB-S2 compliant demodulator. The core accepts I & Q complex baseband samples from an external RF front-end through dual-ADCs. The demodulator output is a sequence of symbols, nominally positioned at the specified constellation points, intended to drive an external LDPC / BCH soft-decision FEC decoder to recover the MPEG transport stream data.
In order to deliver excellent performance, the design utilizes multiple gain control stages within the data path to maximize dynamic range. Up to four sets of matched root-raised cosine filter coefficients can be incorporated into a given implementation, allowing four excess bandwidth values for the input signal to be selected in software. All aspects of the timing and carrier recovery are fully programmable, including loop filter coefficients and lock detector thresholds. In addition, monitoring registers provide a high degree of software visibility for parameters such as frequency offsets, lock levels and SNR estimation.
The DVB-S2 Demodulator IP Core datapath consists of six distinct sections. These correspond to the Radio Interface, Decimator, Timing Recovery, Adaptive Equaliser, Framing Acquisition, and Carrier Recovery functions. The overall operation of the system is automatically managed by an integrated Finite State Machine controller. Communications with the core is handled by a 32-bit Simple Microprocessor Interface (SMPI).
- Excellent performance
- Supports QPSK, 8PSK, 16APSK & 32APSK modulations
- Supports VCM operation
- Normal and short frame sizes
- 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 code rates
- Simple microprocessor interface (SMPI)
- Data capture and monitoring facilities throughout data path
- Fully synchronous design with single clock