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DVB-S2X Compliant LDPC/BCH Decoder IP Core
The AHA4709D LDPC/BCH forward error correction (FEC) decoder core supports all codes, frame sizes, and interleave schemes set forth in the DVB-S2X specifications for broadcast, interactive, digital satellite news gathering, professional services, and very-low signal-to-noise ratio (VL-SNR) applications. The core allows code and modulation changes on a block-by-block basis to fully support both Adaptive Coding Modulation (ACM) and Variable Coding Modulation (VCM).
The AHA4709D decoder core extends the functionality of the AHA4702 DVB-S2 family of cores by adding finer step MODCODs, new lower-order (BPSK) and higher-order (64, 128, 256 APSK) modulations, a medium 32K block size, and new bit interleaving patterns. The Es/N0 performance at frame error rates of 10^-5 spans from -2.85 to 19.57 dB for 64k blocks and from -9.9 to 12.18 dB for 32K/16K blocks.
The AHA4709D decoder core extends the functionality of the AHA4702 DVB-S2 family of cores by adding finer step MODCODs, new lower-order (BPSK) and higher-order (64, 128, 256 APSK) modulations, a medium 32K block size, and new bit interleaving patterns. The Es/N0 performance at frame error rates of 10^-5 spans from -2.85 to 19.57 dB for 64k blocks and from -9.9 to 12.18 dB for 32K/16K blocks.
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