Low-leakage LDO in TSMC 22ULL to supply logic and analog domains (up to 3.63V input supply)
DXAUI PHY
You can implement the XAUI PHY (excluding the PHY management functions) in hard silicon in Altera Stratix® IV (GX and GT), Stratix II GX, Arria® II GX, and Cyclone® IV GX FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. XAUI PHY can also be implemented in soft IP form in Stratix® V , Stratix IV, Arria V, and Cyclone V FPGAs with serial transceivers. Additionally, for applications requiring 20 Gbps throughput, Altera's XAUI PHY solution can support DXAUI (4x 6.25 Gbps) implementations on Stratix IV (GX and GT) FPGAs. Figure 1 illustrates an example of XAUI PHY in Altera devices.
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Ethernet IP
- Ethernet Switch / Router - Efficient and Massively Customizable
- Gigabit Ethernet 802.3 MAC - Media Access Controller
- 12G Ethernet SerDes PHY
- 16G Ethernet SerDes PHY
- TCP/IP - 10 &25Gbit Ethernet TCP server/client
- Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)