Rambus DPA Resistant Cryptographic Accelerator Core ChaCha20 – Small
Dynamically-Reconfigurable Logic
ART is delivered as IP, allowing anything from an entire ASIC to a part of an SoC or ASSP to benefit from the flexibility and reconfigurability enabled by ART.
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Dynamically-Reconfigurable Logic IP
- Northwest Logic Read-Modify-Write Core from Rambus
- PCI Express 4.0/3.0/2.1/1.1 Support from Rambus
- Northwest Logic CSI-2 Controller Core V2 from Rambus
- Northwest Logic AXI DMA Back-End Core from Rambus
- Northwest Logic HBM2/2E Controller Core from Rambus
- PCI Express 5.0/4.0/3.0/2.1/1.1 Core from Rambus