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E1/T1 Mapper/Framer
Aliathons’s Multi-Channel E1/T1/J1 Framer Core provides a flexible, resource-efficient, high-density programmable logic based solution for PDH interfacing. Running at 155MHz, it is capable of framing and deframing up to 1008/1344 E1/T1 channels (enough for a full OC48/STM16).
Features
- Conforms to ITU G.704/ANSI T1.403.
- Best-in-Class size and performance and supports many hundreds of channels.
- Generates and performs frame synchronization for the following PDH signals: T1 – (ESF/SF), J1, E1 – (CRC/Non-CRC/ G.706 Interworking)
- Calculates and inserts CRC; reports CRC values for T1 (ESF), J1 and E1.
- Frame format of each channel may be configured dynamically and independently.
- Supports independent timing on every channel while providing frame overhead insertion and extraction interfaces.
- Provides frame overhead error injection interface and a byte-wide, frame-aligned timeslot input interface. Implements
- a byte-wide frame aligned payload output interface.
- Accepts multiple input streams, making it ideal for interfacing to channelized VT/TU Mappers or multi-channel LIUs.
- Output data streams may dynamically range between 1 and 8 bits wide, allowing seamless interfacing to SONET/SDH VT/TU mappings.
- Full Overhead and Defect processing per channel including. OOF, AIS, FAS, CRC, E-Bit, RAI, SEF.
- Performance Monitoring counters (FAS, CRC, E-BIT). Upstream/Downstream Consequent Action.
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