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Voltage Domain Interfacing Cells for use between power domains using core transistors.
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E31 Balanced performance and efficiency RISC V core
The SiFive E31 Standard Core is the world's most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow's smart IoT, storage, and industrial applications.
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Block Diagram of the E31 Balanced performance and efficiency RISC V core
RISC-V RISCV RISC V IP
- Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- Low-power 32-bit RISC-V processor
- Compact, efficient 64-bit RISC-V processor with 5-stage pipeline
- 64-bit RISC-V application processor core with 7-stage pipeline
- 64-bit RISC-V application processor core with L2 cache coherence
- 64-bit embedded processor, fully compliant with the RISC-V ISA