The IntelliProp IPC-BL119A-ZM is a highly configurable IP core that provides a method of extending an information block with extra bits to guard against the loss or corruption of data across noisy or unreliable communication channels. The ECC core uses the industry standard BCH class of error correcting codes.
Bose-Chaudhuri-Hocquenghem, or BCH codes are a particular example of linear, cyclic, block codes. They are widely used due to their relatively strong correction capabilities and they can deal with randomly distributed errors. The encoding process for BCH does not introduce any additional latency. The initial step in the correction process generates a single error locator polynomial (ELP). The degree of this ELP indicates how many bits are in error in the code word. If the degree of the ELP is greater than the capability of the code, then too many errors have been received and the code word is flagged as uncorrectable. If the degree is less than or equal to the maximum correction capability, then it is generally possible to find and fix the errors. Once a valid ELP is found, this can be directly used to determine the locations of the bit errors. Since binary BCH codes are used, correcting the identified errors is done by flipping the bit at the error locations. The IPC-BL119A-ZM has the capability to parallelize this search by splitting up the field into multiple segments.
The IntelliProp ECC core can be customized to support a wide range of possible BCH codes. The choice of code will be highly dependent on the requirements of the application, and include factors such as the required block length, correction strength, throughput requirements, available spare area / data overhead, and resources available on the target platform. If the desired BCH configuration is not covered by the below values, please contact IntelliProp to discuss possible options.
- High bandwidth, low latency parallel encode and decode paths
- Configurable number of encode blocks
- Configurable number of decode blocks
- Configurable code word length (K), up to 1024 bytes
- Configurable block size
- Configurable 32, 64, 128, or 256 “FIFO” data interface
- Parallelized encoder
- Parallelized decoder for syndrome calculations
- User selectable error correction values (T)
- User selectable field divisor allows for parallelized error search
- Encrypted RTL code
- Self-checking test bench in Verilog Modelsim (please contact IntelliProp for latest supported Modelsim versions). Other simulators may be supported, please check with IntelliProp.
- Simulation script, vectors, and expected results
- Synthesis or place and route script
- Comprehensive user documentation
- Data Storage devices (SATA, SAS, FLASH)
- Compact DISC
- Two dimensional barcodes
- Satellite communications / telemetry
- Radiowave signal recording
- Wireless communications
- High-speed modems such as ADSL, xDSL, etc.
- Power line standards