eDisplay Port v1.4 Rx PHY IP in 40LL, Silicon Proven in SMIC 40LL

The eDisplay Port v1.4 Rx PHY IP Core caters to chips requiring high-bandwidth communication with minimal power consumption. It serves as a multi-gigabit receiver macro compliant with eDP standards. This adaptable and dependable solution enables data reception speeds reaching 5.4Gbps, optimizing both power usage and die size. It boasts simplicity in production and integration into Video Interface systems. The AUX channel supports a bit rate close to 1Mbps, functioning as a half-duplex, bidirectional channel composed of a single differential pair. Each macro includes an AUX channel with one PLL and bias gen unit, along with multiple receiver channels. Essential functions of the receiver encompass a dedicated equalizer, clock and data recovery (CDR), S2P, and self-test features, with the ability to disable individual channels as needed.

• see the entire eDisplay Port v1.4 Rx PHY IP in 40LL, Silicon Proven in SMIC 40LL datasheet
• get in contact with eDisplay Port v1.4 Rx PHY IP in 40LL, Silicon Proven in SMIC 40LL Supplier