English
You are here:
Efficient high-performance 64bit APU core with SMP up to 8-16 cores
64bit Linux-capable application core with virtual memory, MMU, L1/L2 caches, coherency and SMP support
Features
- High-performance 64bit RISC-V application core
- RV64GC ISA
- Flexible uarch template, 10-12 stage pipeline
- User-, Supervisor- and Machine-mode privilege levels
- Fully-featured memory subsystem with Linux support
- Memory Managements Unit (MMU)
- Page-based virtual memory
- L1 and L2 caches with coherency, HW atomics, ECC
- High-performance IEEE 754-2008 compliant floating-point unit
- AXI4- or ACE- compliant external interface
- Configurable Integrated Programmable Interrupt Controller (IPIC) and PLIC
- up to 1024 IRQs
- Advanced Integrated Debug Controller
- JTAG compliant interface
- HW/SW breakpoints support
- ROM breakpoints support
View Efficient high-performance 64bit APU core with SMP up to 8-16 cores full description to...
- see the entire Efficient high-performance 64bit APU core with SMP up to 8-16 cores datasheet
- get in contact with Efficient high-performance 64bit APU core with SMP up to 8-16 cores Supplier
32-bit MCU
- MCU with integrated 64-bit SRAM controller, Memory Protection Unit and real-time, low latency execution unit, optimized for low cost, low power microcontroller and embedded applications
- High-performance, compact, low-power 32-bit cores for MCU and real-time embedded applications
- Compact 32-bit MCU core for deeply embedded applications and accelerator control
- High-performance MCU core with privilege modes and MPU (32 or 64 bit)
- MCU core with high-performance FPU (32 or 64 bit)
- Entry-level Low-Power 32-bit Processor