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EFLX 1K TSMC eFPGA
The EFLX® 1K Logic IP tile is an eFPGA (embeddable FPGA) IP tile with power management containing 560 Look-Up-Tables (LUTs: each is 6-input, or dual-5-input, with 2 independent outputs with 2 bypassable flip flops) and 5 Kbit RAM, Gen 2.0 XFLX™ interconnect network, multiple clocks & scan: fully reconfigurable in-field at any time. The EFLX 1K Logic tile is silicon proven. EFLX 1K DSP tile is “on demand”.
The EFLX 1K DSP tile has 10 DSP MACs (22x22 multiplier with 48 bit accumulator).
EFLX tiles can be arrayed to create larger arrays. Logic and DSP tiles can be mixed. And RAM can be integrated as well.
EFLX features full connectivity inside the tile, and provides ArrayLinx interconnects at the boundary to concatenate multiple tiles via the expandable network I/Os.
The EFLX 1K tile has 368 input pins and 368 output pins. The I/O pins provide user access to the EFLX tile. Each I/O has a bypassable flip flop. When multiple tiles are concatenated into EFLX arrays, the user I/Os along the abutting edges are disabled (or are used for controlling embedded RAM blocks).
Besides input/output pins, there are clock, configuration, and test/DFT pins. Each tile has an internal power grid which can be connected to the customer’s digital SoC power grid. The tile has power control pins. The tile also has configuration ports to load the bitstream. An AXI or JTAG interface is available for configuration. A clock mesh provides multiple connect points.
Readback circuitry in Gen 2.0 enables configuration bits to be read back anytime to enable checking for soft errors to improve reliability for high-reliability applications. A new test mode enables test times about 100x faster to lower test costs.
The EFLX 1K DSP tile has 10 DSP MACs (22x22 multiplier with 48 bit accumulator).
EFLX tiles can be arrayed to create larger arrays. Logic and DSP tiles can be mixed. And RAM can be integrated as well.
EFLX features full connectivity inside the tile, and provides ArrayLinx interconnects at the boundary to concatenate multiple tiles via the expandable network I/Os.
The EFLX 1K tile has 368 input pins and 368 output pins. The I/O pins provide user access to the EFLX tile. Each I/O has a bypassable flip flop. When multiple tiles are concatenated into EFLX arrays, the user I/Os along the abutting edges are disabled (or are used for controlling embedded RAM blocks).
Besides input/output pins, there are clock, configuration, and test/DFT pins. Each tile has an internal power grid which can be connected to the customer’s digital SoC power grid. The tile has power control pins. The tile also has configuration ports to load the bitstream. An AXI or JTAG interface is available for configuration. A clock mesh provides multiple connect points.
Readback circuitry in Gen 2.0 enables configuration bits to be read back anytime to enable checking for soft errors to improve reliability for high-reliability applications. A new test mode enables test times about 100x faster to lower test costs.
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