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8K TicoRAW Encoder / Decoder for RAW CFA sensor data compression
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eFPGA IP cores for GF 12LP/12LP+ Rad Hard By Design
Using Rad Hard By Design standard cells and design guidelines the silicon-proven EFLX eFPGA is now available, to US Companies, in a Rad Hard by Design version.
The EFLX®4K Logic IP core is an embeddable FPGA IP core containing 2,520 Look-Up-Tables (Each LUT can be used as 6-input, or dual-5-input, with 2 independent outputs with 2 bypassable flip flops) in Reconfigurable Building Blocks (RBBs) and 21 Kbit RAM, an improved XFLX™ interconnect network, multiple clocks & scan: fully reconfigurable in-field at any time.
Each EFLX core is a standalone embedded FPGA. Cores can be arrayed up to at least 8x8 to create arrays >500K LUT4s. Logic and DSP cores can be mixed. And RAM can be integrated as well.
Our improved, Gen 2 XFLX™ programmable interconnect has been optimized for higher performance, especially for large arrays.
EFLX features full connectivity inside the core, and provides ArrayLinx™ interconnects at the boundary to concatenate multiple cores: array sizes are possible from 4,000 LUT4s to >500K LUT4s, with a roadmap to >1M LUT4s.
Gen 2 DFT improvements achieve 99% coverage of all faults & a new configuration load mode for test reduces test times about 100 times faster than Gen 1 to lower test costs.
The EFLX 4K Core has 632 input pins and 632 output pins placed as follows: 64 West, 64 East, 252 North, and 252 South. The I/O pins provide user access to the EFLX core. Each pin has a bypassable flip flop. When multiple cores are concatenated into EFLX arrays, the pins along the abutting edges are disabled (or are used for controlling embedded RAM blocks).
Besides input/output pins, there are clock, configuration, and test/DFT pins. Each Core has an internal power grid which can be connected to the customer’s digital SoC power grid. The Core also has configuration inputs on the West side and configuration inputs on the South side to load the bitstream. An AXI or JTAG interface is available for configuration. A clock mesh provides multiple connect points. The configuration bits can be read back anytime to enable checking for soft errors to improve reliability for high-reliability applications. A new test mode enables test times about 100x faster for lower test cost.
In addition to special Rad Hard by Design standard cells for storage elements, design techniques were applied to clock and reset circuits to mitigate the impact of Single Event upsets. Synopsys Premier can be used to further reduce susceptibility to Single Event Upsets by triplicating critical portions of the RTL with voting logic, if desired.
The EFLX®4K Logic IP core is an embeddable FPGA IP core containing 2,520 Look-Up-Tables (Each LUT can be used as 6-input, or dual-5-input, with 2 independent outputs with 2 bypassable flip flops) in Reconfigurable Building Blocks (RBBs) and 21 Kbit RAM, an improved XFLX™ interconnect network, multiple clocks & scan: fully reconfigurable in-field at any time.
Each EFLX core is a standalone embedded FPGA. Cores can be arrayed up to at least 8x8 to create arrays >500K LUT4s. Logic and DSP cores can be mixed. And RAM can be integrated as well.
Our improved, Gen 2 XFLX™ programmable interconnect has been optimized for higher performance, especially for large arrays.
EFLX features full connectivity inside the core, and provides ArrayLinx™ interconnects at the boundary to concatenate multiple cores: array sizes are possible from 4,000 LUT4s to >500K LUT4s, with a roadmap to >1M LUT4s.
Gen 2 DFT improvements achieve 99% coverage of all faults & a new configuration load mode for test reduces test times about 100 times faster than Gen 1 to lower test costs.
The EFLX 4K Core has 632 input pins and 632 output pins placed as follows: 64 West, 64 East, 252 North, and 252 South. The I/O pins provide user access to the EFLX core. Each pin has a bypassable flip flop. When multiple cores are concatenated into EFLX arrays, the pins along the abutting edges are disabled (or are used for controlling embedded RAM blocks).
Besides input/output pins, there are clock, configuration, and test/DFT pins. Each Core has an internal power grid which can be connected to the customer’s digital SoC power grid. The Core also has configuration inputs on the West side and configuration inputs on the South side to load the bitstream. An AXI or JTAG interface is available for configuration. A clock mesh provides multiple connect points. The configuration bits can be read back anytime to enable checking for soft errors to improve reliability for high-reliability applications. A new test mode enables test times about 100x faster for lower test cost.
In addition to special Rad Hard by Design standard cells for storage elements, design techniques were applied to clock and reset circuits to mitigate the impact of Single Event upsets. Synopsys Premier can be used to further reduce susceptibility to Single Event Upsets by triplicating critical portions of the RTL with voting logic, if desired.
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