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eFPGA IP cores for GF 12LP/LP+/14LPP
The EFLX4K Logic IP core is an eFPGA IP core contains 4K LUT4, 21Kb of Distributed Memory and has 632 input pins and 632 output pins.
The EFLX4K DSP IP core is identical except some LUTs are replaced with MACs: 3K LUT4s, 1Kb of Distributed Memory, 40 MACs (22x22 multiplier with 48 bit accumulator and pre-adder; pipelined 10 in a row).
EFLX4K Logic and DSP cores can be interchangeably arranged in arrays up to 500K LUT4s, with optional integrated RAM of any kind.
The EFLX4K GlobalFoundries 14LPP validaiton chip is in characterization over process/voltage/termpature. 12LP/12LP+ is GDS compatible with faster AC timing
The EFLX4K DSP IP core is identical except some LUTs are replaced with MACs: 3K LUT4s, 1Kb of Distributed Memory, 40 MACs (22x22 multiplier with 48 bit accumulator and pre-adder; pipelined 10 in a row).
EFLX4K Logic and DSP cores can be interchangeably arranged in arrays up to 500K LUT4s, with optional integrated RAM of any kind.
The EFLX4K GlobalFoundries 14LPP validaiton chip is in characterization over process/voltage/termpature. 12LP/12LP+ is GDS compatible with faster AC timing
Features
- DFT 99% total fault coverage.
- Utilization typically 90%.
Deliverables
- Front-end Design view (with NDA)
- Encrypted Verilog Model
- LIB
- Footprint LEF
- Detailed datasheet & DSP User’s Guide
- Silicon validation report
- EFLX Compiler evaluation version
- Back-end Design Views (with License)
- Verilog Model
- GDS-II
- CDL/Spice netlist
- Integration guidelines
- Integration assistance as needed
- EFLX Compiler bitstream generation version
- Test vectors
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