The EFLX4K Logic IP core is an eFPGA IP core contains 4K LUT4, 21Kb of Distributed Memory and has 632 input pins and 632 output pins.
The EFLX4K DSP IP core is identical except some LUTs are replaced with MACs: 3K LUT4s, 1Kb of Distributed Memory, 40 MACs (22x22 multiplier with 48 bit accumulator and pre-adder; pipelined 10 in a row).
EFLX4K Logic and DSP cores can be interchangeably arranged in arrays from 1x1 to at least 7x7, with optional integrated RAM of any kind.
The EFLX4K TSMC16FFC eFPGA is silicon proven and validated on TSMC Online. A 200K LUT chip has been fabricated and is available as a hardware evaluation board now. Other variations are GDS compatible with faster AC.
- DFT 99% total fault coverage.
- Utilization typically 90%.
- Only 7 metal layers are used by the IP cores so EFLX is compatible with almost all of the dozens of TSMC 16FFC/FF+ metal stacks.
- The TSMC16FFC GDS is compatible with TSMC12FFC: only the timing is re-run. Now also compatible with 16FFC+/12FFC+.
- Front-end Design view (with NDA)
- Encrypted Verilog Model
- Footprint LEF
- Detailed datasheet & DSP User’s Guide
- Silicon validation report
- EFLX Compiler evaluation version
- Back-end Design Views (with License)
- Verilog Model
- CDL/Spice netlist
- Integration guidelines
- Integration assistance as needed
- EFLX Compiler bitstream generation version
- Test vectors