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Embedded FPGA cores in TSMC 22ULP/28HPC/HPC+
The EFLX4 Logic IP core is an embeddable FPGA IP core containing 4K LUT4s, 21Kb RAM, XFLX interconnect network, multiple clocks & scan: fully reconfigurable in-field at any time.
The EFLX-2.5K DSP core is identical except it has 3K LUT4s with 40 DSP MACs (22x22 multiplier with 48 bit accumulator). It is compatible with the Logic core so it can be mixed with it in arrays.
The cores can be used standalone or arrayed in square or rectangular arrays up to 500K LUT4s.
Just 6 metal layers are used so we are compatible with almost any metal stack.
The EFLX-2.5K DSP core is identical except it has 3K LUT4s with 40 DSP MACs (22x22 multiplier with 48 bit accumulator). It is compatible with the Logic core so it can be mixed with it in arrays.
The cores can be used standalone or arrayed in square or rectangular arrays up to 500K LUT4s.
Just 6 metal layers are used so we are compatible with almost any metal stack.
Features
- Technology: TSMC 28nm HPC/HPC+ & 22nm ULP
- Metal Utilization: 6 metal layers
- Nominal Supply Voltage (Vj): 0.8, 0.9 Vj
- Junction Temperature (°C): −40 to 125 Tj
- Leakage Power (mW): 3 (at 25°C, 0.9V, TT)
- Area (mm2): 1.6
- Clock inputs: 1 to 8
- Input and Output pins : 632 input & 632 output
- Logic Core: 4K LUT4, 21Kb Distributed Memory
- DSP Core: 3K LUT4, 1Kb Distributed Memory, 40 MACs (22x22)
- Arrays: 1×1 to 7×7, any rectangle or square shape
- Design-for-Test Support: Yes, 99% total fault coverage
- Utilization: typically 90%
Deliverables
- Front-end Design view (with NDA)
- Encrypted Verilog Model
- LIB
- Footprint LEF
- Detailed datasheet & DSP User’s Guide
- Silicon validation report
- EFLX Compiler evaluation version
- Back-end Design Views (with License)
- Verilog Model
- GDS-II
- CDL/Spice netlist
- Integration guidelines
- Integration assistance as needed
- EFLX Compiler bitstream generation version
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