MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
eMMC 5.1 Host Controller
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Block Diagram of the eMMC 5.1 Host Controller IP Core
emmc 5.1 host IP
- SD 4.1 / SDIO 4.0 / eMMC 5.1 Host Controller
- SD 5.1 / eMMC 5.1 Host Controller IP
- eMMC 5.1 /SD-SDIO3.0 Host Controller & PHY
- eMMC 5.1 Device Controller
- eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS
- Low-power SD/eMMC host controller IP provides advanced high-performance 32- and 64-bit AXI interface to the SoC