400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28 HPC-EW
These I/O PADs are compliant with the eMMC 5.1 HS400 specification for use in TSMC’s 28nm HPM process. The I/O PADs integrate seamlessly with Arasan’s eMMC 5.1 host controller IP. These PADs address the need for applications requiring high speed as well as low leakage power. eMMC 5.1 HS400 implementation requires a hard PHY for aligning clock edges.
Arasan’s eMMC Total IP which includes the eMMC Controller IP and the eMMC PHY IP have achieved the Automotive Safety Integrity Level B, the architectural metrics SPFM (Single Point Fault Metric) and LFM (Latent Fault Metric) certification, allowing customers to create ISO 26262-compliant SoCs for ADAS and autonomous driving applications.
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