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Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC with AMBA AXI User Interface
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eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPC-NS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core voltage of 1.1V and I/O voltage of 1.8/3.3V in the TSMC 28nm HPC-NS process.
These I/O PADs are compliant with the eMMC 5.1 HS400 specification for use in TSMC’s 28nm HPC-NS process. The I/O PADs integrate seamlessly with Arasan’s eMMC 5.1 host controller IP. These PADs address the need for applications requiring high speed as well as low leakage power. eMMC 5.1 HS400 implementation requires a hard PHY for aligning clock edges.
These I/O PADs are compliant with the eMMC 5.1 HS400 specification for use in TSMC’s 28nm HPC-NS process. The I/O PADs integrate seamlessly with Arasan’s eMMC 5.1 host controller IP. These PADs address the need for applications requiring high speed as well as low leakage power. eMMC 5.1 HS400 implementation requires a hard PHY for aligning clock edges.
Features
- • Suitable for Transmitter, Receiver, and Data Strobe pins
- VCORE Pre driver voltage
- Min 0.99V
- Typ 1.1V
- Max 1.21V
- VCCQ Post driver voltage
- Min 1.72/2.7V
- Typ 1.8/3.3V
- Max 1.98/3.6V
- TJ Junction temperature
- Min -20cC
- Typ 25cC
- Max 100oC
- VIMAX Maximum input voltage
- 3.7V
- Supports 5 drive strength types [0, 1, 2, 3, 4]
Benefits
- Silicon proven, fully compliant core
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
- Unencrypted source code allows easy implementation
- Reuse Methodology Manual guidelines (RMM) compliant verilog code
Deliverables
- GDSII database
- LVS Netlist
- Physical Abstract Model (LEF)
- Timing Models
- Behavioral Models
- Design Integration Guide
- Technical Documentation
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