eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPC-NS
These I/O PADs are compliant with the eMMC 5.1 HS400 specification for use in TSMC’s 28nm HPC-NS process. The I/O PADs integrate seamlessly with Arasan’s eMMC 5.1 host controller IP. These PADs address the need for applications requiring high speed as well as low leakage power. eMMC 5.1 HS400 implementation requires a hard PHY for aligning clock edges.
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