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High-Speed, High-Density and Low Power Memory Compilers and Logic Libraries for GLOBALFOUNDRIES 40LP
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Emulation of RF and channel impairments in Verilog
The BAY9 Virtual RF (VRF) is an IP core written in Verilog, that allows to emulate most system aspects of a typical RF transmission. When connected to a physical layer (PHY) core, the VRF IP core replaces a real RF device between TX-DAC output and RX-ADC input.
Features
- DAC emulation - request p samples every q clock cycles
- IQ imbalance + DC offset
- PA amplitude compression and phase shift
- FIR type fading channel
- Frequency + sampling clock offset
- Additive White Gaussian Noise
- RX gain control with arbitrary definition of attenuation, pin setting, and delay
- Available as Verilog source code without vendor specific IP cores
Benefits
- Test and verify PHY implementations in real time
- Optimize parameters
- Create BER/FER curves in a fast and reproducible way
- Avoid the effort to connect a real RF
Deliverables
- Verilog source code
- Matlab/Octave control functions
- Documentation
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