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PCIe 2.0 PHY, TSMC 16FFC, FFPGL, FFPL x1, x2, x4, x8 North/South (vertical) poly orientation
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Endpoint for Gen1 PCI Express
Virtex-5 FPGA, Gen1 PCI Express
The Xilinx Endpoint solution for Gen PCI Express® includes a PCI Express 1-lane, 4-lane, and 8-lane complete endpoint core and a PCI Express PIPE Interface Protocol Layer core. In addition a PCI Express Endpoint Development Kit is also available. These solutions can be used in communication, multimedia, server and mobile platforms and enables applications such as high-end medical imaging, graphics intensive video games, DVD quality streaming video on the desktop and 10 Gigabit Ethernet interface cards. This core combined with other Xilinx connectivity solutions help customers preserve their investment in older technologies by allowing seamless bridging to other standard and proprietary interfaces.
The Xilinx Endpoint solution for Gen PCI Express® includes a PCI Express 1-lane, 4-lane, and 8-lane complete endpoint core and a PCI Express PIPE Interface Protocol Layer core. In addition a PCI Express Endpoint Development Kit is also available. These solutions can be used in communication, multimedia, server and mobile platforms and enables applications such as high-end medical imaging, graphics intensive video games, DVD quality streaming video on the desktop and 10 Gigabit Ethernet interface cards. This core combined with other Xilinx connectivity solutions help customers preserve their investment in older technologies by allowing seamless bridging to other standard and proprietary interfaces.
Features
- Protocol and electrically compatible
- Complete endpoint solution includes physical, link and transaction, and configuration management modules
- Both 8-lane and 4-lane configurations auto negotiate down to a 1-lane configuration
- Supports packet-oriented LocalLink Interface
- Synchronous point-to-point communication
- Upstream and downstream flow control
- Fully compliant with PCI Express transaction ordering rules
- Efficient link bandwidth utilization
- Error detection and recovery
- Supports maximum payload of 512 bytes
- Design verified by a Xilinx proprietary testbench
- Tested at PCI-SIG compliance workshop and included on PCI Express Integrators List
- PCI Express Xilinx Development Kit available from NitAl
View Endpoint for Gen1 PCI Express full description to...
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