RSA-ECC Public Key Accelerator Engine, 8K ops/sec, DPA & Fault Injection Resistant
Energy Efficient AI & DSP processor in edge computing devices
It has been designed to achieve the lowest power consumption, either with Cores only having 4 pipeline stages and which can be individually clock gated when unused or using Shared Data Memory accessed through a low latency interconnect rather than Data Caches.
Thanks to its different configurability parameters, it can be tailored to exactly match final application use case.
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Block Diagram of the Energy Efficient AI & DSP processor in edge computing devices
