English
You are here:
Energy efficient, small footprint, excellent code density, 32 bit microcontroller
The APS23 is a fully 32 bit general purpose CPU with excellent code density, designed specifically to meet the needs of embedded systems.
The APS23 is an enhanced version of the APS3R, with considerable improved code density for a slight increase in silicon area. The instructions are 16, 24 and 32 bits in length giving excellent code density. The pipeline features out-of-order execution enabling nearly all instructions to execute in a single cycle, including loads and stores. Interrupts are fully vectored and the architecture ensures a minimum of software overhead in task switches. The processor was designed to execute high level languages, notably C, with ease. The software application can be entirely realised in C, interrupt routines included. The entire GNU GCC toolsuite has been ported to this architecture and is available free of charge.
The APS23 is an enhanced version of the APS3R, with considerable improved code density for a slight increase in silicon area. The instructions are 16, 24 and 32 bits in length giving excellent code density. The pipeline features out-of-order execution enabling nearly all instructions to execute in a single cycle, including loads and stores. Interrupts are fully vectored and the architecture ensures a minimum of software overhead in task switches. The processor was designed to execute high level languages, notably C, with ease. The software application can be entirely realised in C, interrupt routines included. The entire GNU GCC toolsuite has been ported to this architecture and is available free of charge.
Features
- Energy Efficient RISC Core
- Harvard architecture
- Excellent Code Density
- 2.79 DMIPS/MHz
- 3-stage pipeline
- Low Power
- High Clock Frequency (> 400MHz in 90nm)
- Integer Multiply (sequential or parallel)
- Up to 250 Low Latency Vectored Interrupts
Benefits
- High performance CPU
- Tiny silicon footprint, less silicon area
- Low Power, longer battery life
- Good Code Density, less Flash memory required
- High maximum clock frequency, more performance, more time sleeping
- Dual-Core Capable, more performance without exploding consumption
- RTOS support: FreeRTOS, uCLinux, uCOS II, uCOS III
- Full Development Environment
- Optional Ethernet 10/100 MAC and USB2.0 Peripheral
- Optional JTAG-Ethernet Debug Solution
Deliverables
- Full Verilog Source Code
- Full Toolchain
- Graphical Development Environment
- Debugger
- Standard Peripherals
- Full Documentation
- Complete Integration Guide
Applications
- Internet of Things (IoT)
- Wireless e.g. Bluetooth, Bluetooth LE
- Always on, always listening subsystems
- Card reader systems
- Smart cards
- Smart sensors
- Touchscreen controller devices
Block Diagram of the Energy efficient, small footprint, excellent code density, 32 bit microcontroller
View Energy efficient, small footprint, excellent code density, 32 bit microcontroller full description to...
- see the entire Energy efficient, small footprint, excellent code density, 32 bit microcontroller datasheet
- get in contact with Energy efficient, small footprint, excellent code density, 32 bit microcontroller Supplier
CPU
- Mid-range, feature-rich 64-bit MIPS CPU
- CPU Designed for the Next Generation of High Performance Wireless Communications and Networking
- AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
- RISC-V Processor - RV12 - 32/64 bit, Single Core CPU
- High performance, flexible, 32 bit Energy Efficient Embedded Microcontroller
- High performance, flexible, extendible 32 bit microcontroller core featuring excellent code density