Mobiveil's Enhanced Secure Digital Memory Controller is a highly flexible and configurable design targeted for consumer applications like digital cameras, mobile phones, tracking devices, tablet computers, gaming etc. The controller architecture is carefully tailored to achieve scalable performance through multiple data transfer modes, and low silicon footprint.
eSDHC is part of Mobiveil’s Storage and Memory controller family of IP solutions which also includes DDR 4/3, LPDDR 2/3, UNEX, and IFC IP cores.
The controller’s simple and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications. Mobiveil solution provides configurability through data path, and frequencies.
eSDHC controller leverages Mobiveil’s years of experience in HyperTransport, PCI, PCIe and RapidIO technologies and the expertise in creating system validated IP solutions with RTL, synthesis, simulation, board and software elements to offer lowest risk in terms of compliance and inter operability.
- Compliant with AXI V1.0 Specification
- Conforms to the SD Host Controller Standard Specification version 3.0
- Compatible with the MMC System Specification version 4.5
- Compatible with the SD Memory Card Physical Layer Specification version 3.01
- Compatible with the SD - SDIO Card Specification version 3.0
- Designed to work with SD Memory, SDIO, SD Combo, MMC, and their variants like mini, micro, embedded etc.
- Card bus clock frequency up to 208 MHz
- Supports 1-bit / 4-bit SD and SDIO modes, 1-bit / 4-bit / 8-bit MMC modes,
- Supports Single Block, Multi Block read and write data transfer and block sizes of 1 ~ 2048 bytes
- Supports both synchronous and asynchronous abort
- Supports pause during the data transfer at block gap
- Supports SDIO Read Wait and Suspend Resume operations
- Supports Auto CMD12 and Auto CMD23 for multi-block transfer
- Supports SDIO Asynchronous Interrupt
- Supports clock divider with finer granularity i.e. with values 1,2,3....1024 or 1,2,4,8...2048
- Supports Standard, High and Extended Capacity card types
- Supports SD UHS-1 speed modes: SDR12, SDR25, SDR50, SDR104, DDR50
- Supports MMC HS200 and DDR mode
- Superior architecture-optimized for high performance, low power and low gate count
- Feature rich, highly flexible, scalable, configurable and timing friendly design
- Ease of integration
- Verified with leading VIP
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
Block Diagram of the Enhanced Secure Digital Host Controller IP Core