Enhanced SPI Master / Slave Controller w/FIFO (APB, AHB, or AXI Bus)
The DB-eSPI-MS contains Transmit/Receive FIFOs and Finite State Machine control with status & interrupt capability to fully off-load from the microprocessor the transfer of data over the SPI Bus. Optionally, the user can transfer transmitted or received data from the SPI Bus to user memory via an optional DMA Controller.
The DB-eSPI-MS supports the addition of Enhanced SPI (eSPI) bus transfers to the standard SPI Master/Slave Controller.
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Block Diagram of the Enhanced SPI Master / Slave Controller w/FIFO (APB, AHB, or AXI Bus)
