Enhanced SPI Master / Slave Controller w/FIFO (APB, AHB, or AXI Bus)

The Digital Blocks DB-eSPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-eSPI-MS contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external SPI Master/Slave devices.

The DB-eSPI-MS contains Transmit/Receive FIFOs and Finite State Machine control with status & interrupt capability to fully off-load from the microprocessor the transfer of data over the SPI Bus. Optionally, the user can transfer transmitted or received data from the SPI Bus to user memory via an optional DMA Controller.

The DB-eSPI-MS supports the addition of Enhanced SPI (eSPI) bus transfers to the standard SPI Master/Slave Controller.

• see the entire Enhanced SPI Master / Slave Controller w/FIFO (APB, AHB, or AXI Bus) datasheet
• get in contact with Enhanced SPI Master / Slave Controller w/FIFO (APB, AHB, or AXI Bus) Supplier