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Scalable, On-Die Voltage Regulation for High Current Applications
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Enhanced UART with FIFOs and Synchronous CPU I/F
The Mentor Graphics M16550S core provides a fully programmable UART that is functionally compatible with the NS 16550AF device. Like the NS 16550AF, the M16550S supports transmission in word lengths of from five to eight bits, together with an optional parity bit and 1, 1½, or 2 stop bits. It also includes two 16-byte FIFOs -one for transmit and one for receive, a 16-bit programmable baud rate generator, an 8-bit scratch register and two DMA handshake lines, which may be configured either to support single-byte transfers (DMA Mode 0) or multiple-byte transfers (DMA Mode 1). Unlike the NS 16550AF, the M16550S offers a synchronous CPU interface. This interface is compatible with the Peripheral Virtual Component Interface (PVCI) defined by VSIA and so allows the core to be readily interfaced to a range of popular on-chip buses such as the AMBA bus and the buses associated with the IBM CoreConnect™ architecture.
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