CoreEDAC is an RTL generator that produces an Microsemi FPGA-optimized error detection and correction (EDAC) core. In many applications, storage elements like SRAM are susceptible to soft (transient) errors caused by heavy ions. These errors can be detected and corrected by employing Error Correction Codes (ECCs). CoreEDAC uses ECCs to incorporate redundancy in data forming codewords that are stored in memory. When recovering data, CoreEDAC first determines if a message read from the RAM is valid. If an error is detected, the decoder finds a valid message that is most similar to the one read and corrects the error.
The core can generate EDAC circuitry for both internal (on-chip) and external RAM blocks. For ease of use, the core enables a user to generate the logic integrated with an on-chip RAM.
- Microsemi FPGA-optimized RTL core generator
- Two modes:
- EDAC with internal RAM
- EDAC encoder and decoder generation
- Optional RAM scrubbing
- Parameterizable refresh (scrubbing) rate
- Flexible user data size from 4 to 64 bits
- User-defined pipeline options to enhance EDAC throughput
- Optional triple EDAC redundancy
Block Diagram of the Error Detection and Correction IP Core