4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
Error Detection and Correction
The core can generate EDAC circuitry for both internal (on-chip) and external RAM blocks. For ease of use, the core enables a user to generate the logic integrated with an on-chip RAM.
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Block Diagram of the Error Detection and Correction IP Core
![Error Detection and Correction Block Diagam](http://www.design-reuse.com/sip/blockdiagram/17073/9-main-Error-Detection-and-Correction.jpg)