Ethernet 1G/10G flexiMAC MACO Core
The flexiMAC core assists the FPGA designer’s efforts by providing pretested, reusable functions that can be easily plugged in, freeing designers to focus on their unique system architecture. These blocks eliminate the need to “re-invent the wheel,” by providing either an industry-standard Layer 2 flexible packet framer and parser or a Layer 1 multi-protocol functionality of the Physical Coding Sublayer (PCS) module. This proven core is optimized utilizing the LatticeSCM device’s MACO architecture, resulting in fast, small cores that utilize the latest architecture to its fullest.
Software Requirements
* ispLEVER version 7.0 or later
* MACO design kit
* MACO license file
View Ethernet 1G/10G flexiMAC MACO Core full description to...
- see the entire Ethernet 1G/10G flexiMAC MACO Core datasheet
- get in contact with Ethernet 1G/10G flexiMAC MACO Core Supplier
Block Diagram of the Ethernet 1G/10G flexiMAC MACO Core
FPGA IP
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- Ethernet Switch / Router IP Core - Efficient and Massively Customizable
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- CXL 2.0 Agilex FPGA Acclerator Card
- Secure-IC's Securyzr(TM) AES-GCM Multi-Booster Réduire la liste des FPGA aux noms des gammes
- CXL 2.0 Dual Mode Controller