Ethernet MAC 10G/25G
The core is highly configurable and easy interfacing with Comcores IEEE 1588 Timestamping Unit (TSU) and 10G/25G PCS solutions.
The Ethernet MAC Core, on the Client side, implements a 64-bit AXI-S Client interface while having a standard 64-bit XGMII interface on the PHY side.
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Block Diagram of the Ethernet MAC 10G/25G IP Core

Ethernet IP
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- Ethernet Switch / Router IP Core - Efficient and Massively Customizable
- 25G Multi Rate SerDes PHY - TSMC 28nm HPC+
- 32G Multi Rate SerDes PHY - GlobalFoundries 22FDX
- Gigabit Ethernet 802.3 MAC - Media Access Controller
- UDP/IP - 10&25Gbit/s Ethernet UDP/IP Offload Engine