Ethernet MAC 40G/100G
The core is highly configurable and easy interfacing with Comcores IEEE 1588 Timestamping Unit (TSU) and 40G/100G PCS solutions.
The Ethernet MAC Core, on the Client side, implements a 256-bit AXI-S Client interface while having a standard 256-bit CGMII interface on the PHY side.
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Block Diagram of the Ethernet MAC 40G/100G IP Core

Ethernet IP
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
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- Ethernet Switch / Router IP Core - Efficient and Massively Customizable
- 32G Multi Rate SerDes PHY - GlobalFoundries 22FDX
- 100BASE-T1 automotive ethernet PHY
- 1000BASE-T1 & 100BASE-T1 automotive ethernet combo PHY