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Serial Peripheral Interface - Master/Slave with single, dual, quad and octal SPI Bus support
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Ethernet MAC & PCS 10G/25G
Comcores 10G/25G Ethernet MAC and PCS is a silicon agnostic implementation of the IEEE 802.3 Ethernet Layer 2 and PCS layer. The IP core performs the Link function of the 10G/25G Ethernet Standard and is a low latency cut-through or store-and-forward implementation reaching best in market results while still keeping size at a minimum. The core is richly featured, fully configurable and supports IEEE1588.
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Block Diagram of the Ethernet MAC & PCS 10G/25G IP Core
Ethernet IP
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- Ethernet Switch / Router IP Core - Efficient and Massively Customizable
- Gigabit Ethernet 802.3 MAC - Media Access Controller
- TCP/IP - 10 &25Gbit Ethernet TCP server/client
- 10 Gb/s full HW stack UDP/IP Transmitter/Receiver
- Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)