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Ethernet Packet Switch 1G

Comcores 1G Ethernet Packet Switch IP core is an advanced switch supporting buffering of large amounts of data in external RAM. The non-blocking Ethernet switch IP core enables fine-grained traffic differentiation for rich implementations of packet prioritization enabling per port and per queue shaping on egress ports.

The switch supports MAC learning, VLAN 802.1Q, multicast and broadcast as well as IEEE 1588 transparency. Each port provides a native interface for GMII Ethernet PHY devices.

Features

Delivers Performance

QoS features such as classification, queuing and priorities included
Automatic MAC address learning and aging
Supports buffering of up to 128 MB in DDR
Extensive statistic reporting

Easy to use

Solid Verification Environment
Very easy integration on Xilinx evaluation platforms
GMII interfaces for attaching external Physical Layer devices (PHY)

Highly Configurable

Buffer size fully configurable
Configurable scheduling (round-robin, strict priority, etc.)
Configurable tagging

Silicon Agnostic

Designed in Verilog and targeting any RTL implementation like ASICs, ASSPs and FPGAs

Deliverables

The IP core comes deeply verified and with an extensive documentation that, among others,includes Product Brief, User Manual and Programming Register Specification.The core will by default come in an encrypted format. Source code option is available.

Block Diagram of the Ethernet Packet Switch 1G IP Core

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