Ethernet PCS 10G/25G
The IP-core has been optimized for size and offers an XGMII interface on one side and a 64-bit interface on the PMA-side.
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Block Diagram of the Ethernet PCS 10G/25G IP Core

Ethernet IP
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- Ethernet Switch / Router - Efficient and Massively Customizable
- Gigabit Ethernet 802.3 MAC - Media Access Controller
- TCP/IP - 10 &25Gbit Ethernet TCP server/client
- Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)
- Gigabit Ethernet PHY (Modification Right)