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Ethernet Subsystem 10G/25G
Comcores Ethernet Subsystem IP is a silicon-agnostic, easy-to-use integration of specific IP blocks. The subsystem IP is richly featured, highly configurable and comes in different variations of Ethernet MAC, Ethernet PCS, IEEE 1588 PTP (with Time Stamping Unit), DMA and can include TSN features.
The subsystem IP is ready for 5G applications, and is thoroughly tested and verified, thus reducing your risks and will save development time as the solution will reduce your design and integration efforts.
The subsystem IP is ready for 5G applications, and is thoroughly tested and verified, thus reducing your risks and will save development time as the solution will reduce your design and integration efforts.
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Block Diagram of the Ethernet Subsystem 10G/25G IP Core
DMA core IP
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 4.0 Controller with AMBA AXI interface
- AMBA Parameter Configurable Multi-Channel DMA Controller (typically 1 to 256)
- AHB Multi-Channel DMA Controller
- DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
- DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List