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Ethernet Subsystem 10G/25G
Comcores Ethernet Subsystem IP is a silicon-agnostic, easy-to-use integration of specific IP blocks. The subsystem IP is richly featured, highly configurable and comes in different variations of Ethernet MAC, Ethernet PCS, IEEE 1588 PTP (with Time Stamping Unit), DMA and can include TSN features.
The subsystem IP is ready for 5G applications, and is thoroughly tested and verified, thus reducing your risks and will save development time as the solution will reduce your design and integration efforts.
The subsystem IP is ready for 5G applications, and is thoroughly tested and verified, thus reducing your risks and will save development time as the solution will reduce your design and integration efforts.
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Block Diagram of the Ethernet Subsystem 10G/25G IP Core
DMA core IP
- AXI DMA Back-End Core
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- AXI4 Memory-Mapped to/from AXI4-Stream DMA
- DMA Back-End Core