Ethernet Switch / Router - Efficient and Massively Customizable
Packet Architects can provide IP cores with a full range of Ethernet switching and routing features such as IPv4/IPv6 routing, L2 switching, MPLS switching, advanced VLAN handling, classification, automatic learning etc.
The core is built around a shared buffer memory architecture providing wire-speed switching and routing on all ports without head of line blocking. It offers dynamic allocation of packet buffers per port and priority to avoid starvation due to over-allocation. Advanced QoS features allow the most timing critical packets to get minimal delay while providing fairness between traffic classes.
No initial software setup is required and due to the hardware learning for MAC addresses the core is ready to receive and forward Ethernet frames immediately once powered up. There is a high performance processor interface for register configuration, and a high performance dedicated CPU port for slow path processing of packets.
The design is optimized for both FPGA and ASIC technology but does not have any dependencies on the underlying technology. If the target technology has TCAMs these can be utilized.
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Block Diagram of the Ethernet Switch / Router - Efficient and Massively Customizable

ethernet IP
- Gigabit Ethernet 802.3 MAC - Media Access Controller
- TCP/IP - 10 &25Gbit Ethernet TCP server/client
- Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)
- Gigabit Ethernet PHY (Modification Right)
- 10 & 25Gbit/s Ethernet UDP/IP Hardware Stack for FPGAs
- EA/MZ Modulator Driver 1.25Gb/s to 11.3Gb/s