4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
Ethernet TSN MAC 10M/100M/1G/2.5G
The TSN MAC enables deterministic low latency and guaranteed jitter for time sensitive applications. The TSN MAC allows flexibility in selecting a subset of standards depending on your application from industrial to automotive.
The feature rich MAC core is a low latency cut-through implementation, while keeping size at a minimum. The core is fully configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Ethernet MAC Core has a standard GMII interface on the PHY side, with MII and RGMII being optional.
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Block Diagram of the Ethernet TSN MAC 10M/100M/1G/2.5G
![Ethernet TSN MAC 10M/100M/1G/2.5G Block Diagam](http://www.design-reuse.com/sip/blockdiagram/46258/20220405042659-main-2021-04-05-1G-TSN-Architecture-diagram.png)
Ethernet MAC IP
- The Synopsys 1.6T Ethernet MAC IP is based on IEEE 802.3-2018 spec for 400Gbps, 800Gbps & 1.6Tbps Ethernet applications
- Synopsys 1.6T Ethernet MAC IP
- Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)
- 100G Ethernet MAC/RS
- 800G/400G/200G Ethernet MAC
- 40G/100G Ethernet PCS/MAC IP Cores