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Everything needed to deploy a Western Digital EH1 superscalar RISC-V core
The SweRV Core EH1 Support package (SCSP) contains everything needed to deploy a Western Digital SweRV™ EH1 core in an integrated circuit providing support for both EDA tool flows and embedded software development. SCSP saves the considerable effort that would be needed to set up EDA flows for the EH1 core from scratch.
The Western Digital SweRV Core™ EH1 is a 2-way superscalar core with a 9-stage pipeline.
The core includes two identical ALUs, a divider and a pipelined multiplier. It is a high-performance embedded core rated at 4.9 CM/MHz.
The SweRV Core Support Package for EH1 is available in both basic free and Pro versions.
The Free version consists of open source deliverables and infrastructure for using open source EDA tools and an SDK. Users can access a forum for support
The Pro version combine open source and commercial deliverables. It provides flows, examples and models for using commercial EDA tools. Codasip provides professional support for this version.
The Western Digital SweRV Core™ EH1 is a 2-way superscalar core with a 9-stage pipeline.
The core includes two identical ALUs, a divider and a pipelined multiplier. It is a high-performance embedded core rated at 4.9 CM/MHz.
The SweRV Core Support Package for EH1 is available in both basic free and Pro versions.
The Free version consists of open source deliverables and infrastructure for using open source EDA tools and an SDK. Users can access a forum for support
The Pro version combine open source and commercial deliverables. It provides flows, examples and models for using commercial EDA tools. Codasip provides professional support for this version.
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Block Diagram of the Everything needed to deploy a Western Digital EH1 superscalar RISC-V core
RISC-V IP
- Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- Low-power 32-bit RISC-V processor
- 64-bit embedded processor, fully compliant with the RISC-V ISA
- Compact RISC-V Processor - 32 bit, 3-stage
- RISC-V processor - 32 bit, 5-stage pipeline
- Linux capable 64-bit RISC-V processor core with 7-stage pipeline