The Y145 core is an exact copy of the Zilog Z80-SIO, having been created using the orginal Zilog schematics under contract for Zilog. That contract grants Systemyde the right to license the design. Because this core is an exact copy of the Zilog design, it is best to refer to the original Zilog documentation for the Z80-SIO for details about the operation of the device.
- Technology-independent Verilog HDL implementation.
- 8-bit CPU interface.
- Two independent full-duplex channels.
- Receivers are quadruply buffered; transnmitters are doubly-buffered.
- Z80-CPU interrupt structure.
- Optional 32-bit CRC.
- Optional direct Interrupt Acknowledge and Return-from-Interrupt inputs.