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EZ80 Microprocessor with Multiply and Accumulator(MACC)
The eZ80™ is ZiLOG’s next-generation Z80™ processor. The multiple operating modes of the processor allows
Z80 and Z180 code to be run in the same application with new code, thus taking advantage of the eZ80’s 16MB
linear addressing space and enhanced instruction set. These features provide you with performance that is
comparable to 16-bit processors with the form factor and power savings of an 8-bit processor. The eZ80 is
completely Z80 code-compatible, which reduces development time. The eZ80 also features a Multiply and
Accumulate engine, which enables you to attack signal-processing applications that require polynomial
calculations, such as basic filters. The eZ80 is internet-ready and ZiLOG can provide a TCP/IP stack for rapid
internet connectivity. The eZ80 also features ZiLOG’s Debug Interface. This two-pin interface allows advanced
debugging features without the cost, difficulty, and unpredictability of an in-circuit emulator. The eZ80 is a
licensable soft core, which allows for rapid integration into any design.
Z80 and Z180 code to be run in the same application with new code, thus taking advantage of the eZ80’s 16MB
linear addressing space and enhanced instruction set. These features provide you with performance that is
comparable to 16-bit processors with the form factor and power savings of an 8-bit processor. The eZ80 is
completely Z80 code-compatible, which reduces development time. The eZ80 also features a Multiply and
Accumulate engine, which enables you to attack signal-processing applications that require polynomial
calculations, such as basic filters. The eZ80 is internet-ready and ZiLOG can provide a TCP/IP stack for rapid
internet connectivity. The eZ80 also features ZiLOG’s Debug Interface. This two-pin interface allows advanced
debugging features without the cost, difficulty, and unpredictability of an in-circuit emulator. The eZ80 is a
licensable soft core, which allows for rapid integration into any design.
Features
- - Improved CPU Performance and Code-Compatible with Z80 Core
- - Z80/Z180 Binary Compatible Instruction Set
- - Illegal instruction trap
- - Additional instructions to work with the MACC
- - Single cycle instruction fetch
- - 16MB Linear Addressing (24-bit Internal registers e.g. IX, IY, HL,
- DE, BC, SP)
- - Multiply and Accumulate Engine (available on various members of
- the eZ80 family)
- - Internet-Ready TCP/IP Stack (available on various members of the
- eZ80 family)
- - ZiLOG Debug Interface (ZDI) Capability
- - Dual stack pointers for extended and native mode
- - NMI and INT0 + 128 Vectored Interrupts
- - 47.61MHz operating frequency in Synthesis and Pre-Layout STA
Benefits
- SoC Integration
- Customization
Deliverables
- Fully synthesizable Verilog RTL source code
- Fully synthesized, scan inserted and scan stitched Netlist
- Synthesis & STA constraints
- Synthesis Scripts
- STA scripts
- Verification Environment
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